In multiprocessor systems, multiple central processing units share a system bus for various transactions, including non-cacheable data transactions for Input/Output operations. For the various transactions the bus has a limited bandwidth that must be shared by the multiple central processors. Accordingly, it is important to reduce the bus bandwidth needed for non-cacheable data transactions of each processor, so that there is more effective bandwidth available for use by other processors in the multiprocessor system and by other types of transactions.
Furthermore in multiprocessor systems, multiple central processing units share cacheable data in memory. This data could exist in several different locations including high speed cache memory as well as main memory. If a particular data at a certain address is most recently modified in one of the memory locations, then the most recently modified data must be identified and available to all CPU's requesting the particular data.
What is needed is an apparatus for efficiently managing Input/Output operations and memory shared by processors in a multiprocessor (MP) system.